programming guide, integer n pll synthesizer 100 - 2800 mhz rev. v2 application note AN3004 ? north america tel: 800.366.2266 ? europe tel: +353.21.244.6400 ? india tel: +91.80.4155721 ? china tel: +86.21.2407.1588 1 visit www.macomtech.com for additional data sheets and product information. m/a-com technology solutions inc. and its affiliates reserve the right to make changes to the product(s) or inform ation contained herein without notice. introduction m/a-com?s surface mount frequency synthesizers integrate a low-noise buffered vco, phase locked loop circuit and low-pass loop filter. the vco output is coupled into the pll circuit where the vco frequency is divided down in a dual-modulus prescaler and 18-bit n counter or feedback divider (5-bit swallow counter and 13-bit programmable divider) to the phase comparison frequency or step size of the pll. this is usually in the range of 10 khz to 5 mhz for most a pplications. the prescaler modulus is 32/33. the external reference oscillator is also divided down in the 14-bit programmable r counter or reference divider to the same phase comparison frequency. the divided vco and divided reference signals are then fed into the phase co mparator, which produces an error signal whose magnitude is proportional to the phase difference between the two signals. the error signal is then passed through a loop filter to produce the desired perfor mance characteristics and the result is a voltage, which is applied to the tuning input of the vco. the frequency of the vco is then steered to the desired frequency, at which point the phase difference in the p hase comparator will be zero. the phases of the divided vco and the divided reference signals are then said to be ?locked? to one another, hence the term phase locked loop. any subsequent phase or frequency perturbation on the vco output results in an error signal at the output of the phase comparator. this error signal in turn produces a modification of the tuning voltage to maintain the phase locked condition. a typical synthesizer block diagram is shown below. programming overview the programmable dividers and counters are serially programmed using a standard 3-wire cmos or ttl interface. the programming data is input using the clock, data and load enable input pins. the clock input latches one bit on the data input into the pll shift register on the rising edge of each clock pulse (msb first). when the load enable input is high the stored data is transferred into the latches. the last two bits are the control bi ts. the data is transferred into the counters as shown below. ref osc. 14-bit r counter phase comparator loop filter 18-bit n counter prescaler 32/33 21-bit shfit register 18-bit function latch clock latch enable data output vco typical block diagram control c2 c1 0 0 r counter 0 1 n counter 1 0 function latch 1 1 initialization data location programming the reference word (r counter) if the control bits are (c2, c1) = (0, 0), data is transferred from the 21-bit shift register into a latch that sets the 14-bit r counter. bits r1 ? r14 hold the reference division ratio. bits r15 ? r18 are for test modes, and should be set to 0 for normal use. bit r19 specifies lock detect (ld) precision and is used in the digital lock detect mode, as described in the function latch section. serial data format is shown on the next page, together with the pro- gramming table for the r counter.
programming guide, integer n pll synthesizer 100 - 2800 mhz rev. v2 application note AN3004 ? north america tel: 800.366.2266 ? europe tel: +353.21.244.6400 ? india tel: +91.80.4155721 ? china tel: +86.21.2407.1588 2 visit www.macomtech.com for additional data sheets and product information. m/a-com technology solutions inc. and its affiliates reserve the right to make changes to the product(s) or inform ation contained herein without notice. r r r r r r r r r r r r r r r r r r r c c 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 2 1 division ratio (r) r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 3 0 0 0 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 0 0 0 0 1 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 16383 1 1 1 1 1 1 1 1 1 1 1 1 1 1 msb lsb 14-bit programmable r counter notes: division ratios less than 3 are prohibited. division ratios from 3 to 16383 are allowed. the maximum step size or phase comparison fre- quency allowable for a given output frequency is given by: u f f min / p ( p ? 1 ) where, u f = phase comparison frequency or step size, f min = minimum synthesizer output frequency and p = prescaler modulus. for example, the maxi- mum step size allowable to programme f min = 1810 mhz using the modulus 32 prescaler would be u f 1810 mhz / (32 x 31) = 1.82 mhz. example the reference division ratio for the programmable r counter is calculated using: r = f ref / u f where, r = r counter division ratio, f ref = refer- ence oscillator frequency and u f = phase com- parison frequency or step size. note that the refer- ence frequency used must be an exact multiple of the required phase comparison frequency. for example, programme the synthesizer to use a phase comparison frequency / step size of 50 khz using a reference frequency of 10 mhz. this would require an r counter division ratio of r = 10 mhz / 50 khz = 200 = 11001000 in binary. selecting the reference word would require (c1, c2) = (0, 0). the complete 21-bit binary reference word to be programmed would then be as below. x 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 msb lsb
programming guide, integer n pll synthesizer 100 - 2800 mhz rev. v2 application note AN3004 ? north america tel: 800.366.2266 ? europe tel: +353.21.244.6400 ? india tel: +91.80.4155721 ? china tel: +86.21.2407.1588 3 visit www.macomtech.com for additional data sheets and product information. m/a-com technology solutions inc. and its affiliates reserve the right to make changes to the product(s) or inform ation contained herein without notice. programming the frequency word (n counter) if the control bits are (c2, c1) = (0, 1), data is transferred from the 21-bit shift register into a 5-bit latch which sets the swallow (a) counter and a 13-bit latch which sets the programmable (b) counter. the go bit, n19, sets the charge pump output current. if n19 = 0, i cp = 250 a if n19 = 1, i cp = 1ma. please refer to individual m/a-com component product specifications for the charge pump current required in each case. the serial data format and the pro- gramming tables for the n counter are shown be- low. example the feedback division ratio for the programmable n counter is calculated using: n = f out / u f where, n = n counter division ratio, f out = synthe- sizer output frequency and u f = phase comparison frequency or step size. note that the output fre- quency must be an exact multiple of the phase comparison frequency. the step size is usually determined by system specif ications or the required channel frequency resolution. go division ratio of the b counter division ratio of the a counter control n n n n n n n n n n n n n n n n n n n c c 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 2 1 lsb division ratio (r) n18 n17 n16 n15 n14 n13 n12 n11 n10 n9 n8 n7 n6 3 0 0 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 0 0 0 1 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 8191 1 1 1 1 1 1 1 1 1 1 1 1 1 13-bit programmable b counter division ratio (r) n5 n4 n3 n2 n1 3 0 0 0 0 0 4 0 0 0 0 0 ? ? ? ? ? ? 8191 1 1 1 1 1 5-bit swallow a counter notes: b division ratios less than 3 are prohibited. b division ratios from 3 to 8191 are allowed. b a control bits (c2, c1) set to (0, 1) to load a and b counters. data is shifted msb first. notes: a division ratios from 0 to 31 are allowed. b a in order to programme the a and b counters the following mathematical relationship is used: n = ( p x b ) + a where, p = modulus of the prescaler (32), b = b counter division ratio determined by the integer of n/p, and a = a counter division ratio determined by the remainder of n/p. for example, programme the synthesizer to an output frequency of 1810 mhz using a phase com- parison frequency or step size of 50 khz. then n counter division ratio n = 1810 mhz / 50 khz = 36200 = ( p x b ) + a. b counter division ratio b = integer of n / p = 36200 / 32 = 1131 = 10001101011 in binary. a counter division ratio a = remainder of n / p = 36200 ? ( 32 x 1131 ) = 8 = 1000 in binary. selecting the frequency word would require (c2, c1) = (0, 1). msb
programming guide, integer n pll synthesizer 100 - 2800 mhz rev. v2 application note AN3004 ? north america tel: 800.366.2266 ? europe tel: +353.21.244.6400 ? india tel: +91.80.4155721 ? china tel: +86.21.2407.1588 4 visit www.macomtech.com for additional data sheets and product information. m/a-com technology solutions inc. and its affiliates reserve the right to make changes to the product(s) or inform ation contained herein without notice. msb lsb x 0 0 1 0 0 0 1 1 0 1 0 1 1 0 1 0 0 0 0 1 the complete 21-bit binary frequency word to be programmed would then be as below. function and initialisation latches both the 18-bit function and initialisation latches write to the same registers. for the function latch, (c2, c1) = (1, 0). for the initialisation latch, (c2, c1) = (1, 1). load- ing the function latch with (c2, c1) = (1, 1) imme- diately followed by an r counter load, then an n counter load, efficiently programmes the control register. setting (c2, c1) = (1, 1) programmes the same function latch as a load with (c2, c1) = (1, 0), and additionally provides an internal reset pulse. this programme sequence ensures that the counters are at load point when the n counter data is latched in and the part will begin counting in close phase alignment. programming the function latch the serial data format is shown below, together wi th the programming table for the function latch. f f f f f f f f f f f f f f f f f f f c c 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 4 3 2 1 2 1 f18 f17-15 f14-11 f10 f9 f8 f7 f6 f5-3 f2 f1 c2 c1 power down mode test modes timeout counter value timeout counter enable fastlock control fastlock enable cp tri- state pd polarity fo/ld control power down counter reset 1 0 msb lsb bit function description f1: the counter reset bit, when activated, allows the reset of both n and r counters. in normal operation this is set to 0. f2, f18: the powerdown bits provide programmable powerdown modes. in normal operation these are both set to 0. f3-5: these bits control the function of the fo/ld out- put of the pll ic. on m/a-com synthesizers, bits (f5, f4, f3) should be set to (0, 0, 1) for digital lock detect or (1, 0, 1) for analog open-drain lock detect. in digital mode, the lock detect output (pin 9 of the synthesizer) goes high when the absolute phase error is <15ns for 3 consecutive phase comparator cycles if bit r19 is low, or 5 consecutive phase com- parator cycles if bit r19 is high. if the absolute phase error >30ns for a single phase comparator cy- cle, lock detect will go low. in analog mode, when the loop is locked, lock detect is high with narrow low pulses at the phase com- parison frequency. when the loop is out of lock, lock detect alternates between high and low, at a rate dependent on the frequency error. an external filter is needed, to turn these conditions into stable high or low states. see application note an3003 for notes on filter design. f6: the phase detector polarity bit should be set to 1. f7: the charge pump tri-state bit should be set to 0 for normal operation. f8: m/a-com synthesizers are not designed to use fast- lock modes, so f8 should be set to 0. f9-14: the fastlock and timeout counter control bits should be set to 0 on m/a-com synthesizers. f15-17: these are for test modes, and should be set to 0 for normal operation. for more detailed information on the operation of the pll ic, please refer to the national semiconductor lmx2326 data sheet.
programming guide, integer n pll synthesizer 100 - 2800 mhz rev. v2 application note AN3004 ? north america tel: 800.366.2266 ? europe tel: +353.21.244.6400 ? india tel: +91.80.4155721 ? china tel: +86.21.2407.1588 5 visit www.macomtech.com for additional data sheets and product information. m/a-com technology solutions inc. and its affiliates reserve the right to make changes to the product(s) or inform ation contained herein without notice. serial data input timing diagram data in parenthesis indicates reference word data. data shifted into register on rising edge of clock pulses, msb first. electrical characteristics vcc = 5.0v -40 c |
